数据采集与处理2011，Vol.26Issue(3)：367-373,7.
基于FPGA的32位RISC微处理器设计
Design of 32-Bit RISC Microprocessor Based on FPGA
刘览 1郑步生 1施慧彬2
作者信息
- 1. 南京航空航天大学电子信息工程学院,南京,210016
- 2. 南京航空航天大学计算机科学与技术学院,南京,210016
- 折叠
摘要
Abstract
A 32-bit RISC microprocessor HP_MIPS which is compatible with the MIPS32 product, is presented in the paper. After the structural analysis of the classic MIPS, the structure of the processor is re-divided. By increasing the pipeline stages a microprocessor data path structure with 8-stage pipeline is designed and an excellent solution for pipeline data hazards is provided. In addition, a pipelines dynamic branch predictor is designed for resolving branch hazards, which not only reduces the CPI of the microprocessor but also prevents the pipeline logic jams to reduce the clock speed of microprocessors. Finally, software emulation and hardware verification are implemented, and it comes out that HP_MIPS is able to run up at 146.62 MHz on FPGA chip.关键词
精简指令集计算机/微处理器/流水线/分支预测Key words
reduce instruction set computer (RISC)/ microprocessor/ pipeline/ branch prediction分类
信息技术与安全科学引用本文复制引用
刘览,郑步生,施慧彬..基于FPGA的32位RISC微处理器设计[J].数据采集与处理,2011,26(3):367-373,7.
