现代电子技术2011，Vol.34Issue(10)：149-151,3.
基于March C+算法的SRAM BIST设计
SRAM BIST Design Based on March C+ Algorithm
摘要
Abstract
In order to increase controllability and ohservability in memory testing and to reduce the testing time, a BIST design hased on March C+ algorithm for a 32-bits SRAM in LEON processor is proposed, in which SRAM fault model and BIST implementation are discussed. The designed BIST circuit can well connect with system. and only increase few I/O ports. Simulation results prove that the BIST design has good fault coverage without increasing chip area.关键词
SRAM/BIST/March C+算法/故障模型Key words
SRAM/ BIST/ March C+ algorithm/ fault model分类
信息技术与安全科学引用本文复制引用
张志超,侯立刚,吴武臣..基于March C+算法的SRAM BIST设计[J].现代电子技术,2011,34(10):149-151,3.基金项目
国家自然科学基金资助项目(60976028) （60976028）
北京工业大学博士启动基金资助项目(X0002012200802) （X0002012200802）
