计算机应用研究2011，Vol.28Issue(2)：587-590,4.DOI:10.3969/j.issn.1001-3695.2011.02.051
基于ARMv4T架构指令集的乘法器设计
Design of multiplier based on instruction set of ARMv4T architecture
摘要
Abstract
Aiming at the two performance targets of speed and area for hardware IP core, this paper proposed the design of multiplier suitable for 32-bit microprocessor, with the idea of multi-cycle multiplier based on adjustable execution cycle.It was compatible with all multiplicative instructions of ARMv4T architecture, simultaneously introduced byte-judgment mechanism which could achieve the instruction in 2 ～ 5 cycles according to the operand' s characteristic.The design adopted Radix-4 Booth encoding, needing only two-level 4-2 compress octree.The base register data of multiply-accumulate came into compressors as a partial product, saving a single execution cycle.The experiment result shows that it owns small chip area, with easy and high-performance configuration.关键词
ARMv4T架构/乘法器/可变执行周期/Radix-4 Booth编码/4-2压缩树分类
信息技术与安全科学引用本文复制引用
陈海民,李峥,杨先文..基于ARMv4T架构指令集的乘法器设计[J].计算机应用研究,2011,28(2):587-590,4.基金项目
国家自然科学基金资助项目(61072047) （61072047）
现代通信国家重点实验室基金资助项目(9140C1106021006) （9140C1106021006）
郑州市创新型科技人才队伍建设工程(096SYJH21099) （096SYJH21099）
