光通信技术2011，Vol.35Issue(3)：40-42,3.
SDH中HDB3编解码电路的FPGA实现
Implement of HDB3 codec circuits by FPGA in SDH system
摘要
Abstract
In the SDH transmission system ,in order to make the waveform meet the requirements of extracting the timing information conveniently and capability of error detection, it chooses the common channel transmission code which is third-order high-density bipolar code (HDB3).This paper aims to introduce the coding and decoding principle of HDB3. The selected FPGA device (ALTERA Corp Cyclone III series) is written by Verilog HDL code in the Quartos II 9.0 environment to accomplish routing and timing simulation. The simulation results and experimental results are consistent with the theoretical output. As the features high integration, low power consumption and repeated programmable of FPGA.关键词
HDB3码/FPGA/SDH/Verilog HDLKey words
HDB3/FPGA/SDH/ Verilog HDL分类
信息技术与安全科学引用本文复制引用
崔洲涓,胡辽林..SDH中HDB3编解码电路的FPGA实现[J].光通信技术,2011,35(3):40-42,3.基金项目
陕西省教育厅科学研究计划(2010JK716)资助. （2010JK716）
