半导体学报2011，Vol.32Issue(1)：108-115,8.DOI:10.1088/1674-4926/32/1/015006
A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology*
A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology*
摘要
Abstract
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.关键词
ultra high-speed/ wide-bandwidth/ folding/ interpolating/ analog-to-digital converterKey words
ultra high-speed/ wide-bandwidth/ folding/ interpolating/ analog-to-digital converter引用本文复制引用
Yu Jinshan,Zhang Ruitao,Zhang Zhengping,Wang Yonglu,Zhu Can,Zhang Lei,Yu Zhou,Han Yong..A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology*[J].半导体学报,2011,32(1):108-115,8.基金项目
Project supported by the National Natural Science Foundation of China (Nos.60906009,60773025),the Postdoctoral Science Foundation of China (No.20090451423),and the National Labs of Analog Integrated Circuits Foundation (No.9140C0901110902). （Nos.60906009,60773025）
