西安电子科技大学学报（自然科学版）2011，Vol.38Issue(2)：146-150,5.DOI:10.3969/j.issn.1001-2400.2011.02.026
一种面向片上网络的多时钟路由器设计
Multi-clock router designed for the network-on-chip
摘要
Abstract
The router is a core element of the NoCs(Network-on-Chips). Aiming at NoC communication issues among different clock domains, the paper proposes a multi-clock router microarchitecture, which applies to 2D mesh topology NoC and uses dual-clock asynchronous FIFOs( First In First Out) instead of cross-clock domain interface circuits in usual routers. Designed by the Verilog HDL, the router's integrated results on FPGA show that it uses fewer resources and operates at a high frequency of up to 475.29MHz, effectively increasing the data transmission rate. Based on SMIC 0. 13μm CMOS technology, by comparing the integrated results of routers with different FIFO depth values, impacts of the buffer size on the router's performance and cost are analyzed further.关键词
片上网络/路由器/多时钟分类
信息技术与安全科学引用本文复制引用
刘毅,杨银堂,周东红..一种面向片上网络的多时钟路由器设计[J].西安电子科技大学学报（自然科学版）,2011,38(2):146-150,5.基金项目
国家杰出青年基金资助项目(60725415) （60725415）
国家自然科学基金资助项目(60676009,60776034) （60676009,60776034）
中央高校基本科研业务费专项资金资助项目(K50510250004) （K50510250004）
