电子学报2011，Vol.39Issue(5)：1165-1168,4.
高性能可编程互连资源设计研究
High Performance Programmable Interconnect Resource Design Investigation
摘要
Abstract
Convertional FPGAs use transistor switch in short range interconnection and bidirectional mid range lines, which would make the interconnection delay grows exponentially with the wire length as the number of Look Up Table(LUT) in CLB increases. In this article, we present an improved high performance routing architecture, whose short, mid and long range lines are improved to make the interconnect resource has a better delay performance when the CLB tends to become larger and contains more programmable logic resource and the area of CLB grows larger, and compare its performance with the conventional FPGA' s routing architecture by modeling and simulation. Through the comparison,we know that using this new architecture,the double lines are average 21.9％ faster,the hex lines are average 21.7％ faster,and the lone lines are average 4％ faster. And this routing architecture has already been used in the FDP2009-2-SOPC FPGA chip,which is designed and taped out by ourselves. And we also have finished the performance test of its routing resources and proved the superiority of our idea.关键词
可编程逻辑器件/可编程互连结构/延迟Key words
programmable logic instrument /programmble routing architecture/delay分类
信息技术与安全科学引用本文复制引用
陈星,王丽云,王元,吴方,王健,陈利光,来金梅..高性能可编程互连资源设计研究[J].电子学报,2011,39(5):1165-1168,4.基金项目
国家自然科学基金(No.60876015) （No.60876015）
国家863高技术研究发展计划(No.2007AA01Z285) （No.2007AA01Z285）
