计算机应用与软件2011，Vol.28Issue(6)：239-241,3.
高性能SRAM的设计与实现
DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE SRAM
摘要
Abstract
In this paper a 64KB SRAM is designed and implemented for the purpose of shorter delay and lower energy consumption. To speed up the decoder the conventional static CMOS gates are modified into SCL and pre-charged gates. Encoding the ECC with 64:72 reduces the circuit size and cell numbers. The capacitance replica is used to generate sense amplifier enabling signals to improve system flexibility.The transistor is used for emulation. Compared to mainstream designs, the SRAM designed in this paper owns an improved delay of 653.7ps and a lower energy consumption of 11.3mw.关键词
SRAM/Block/ECC/灵敏放大器Key words
SRAM/ Block/ ECC/ Sense amplifier引用本文复制引用
吴耀辉,胡涣章,梁丰,蔡宇..高性能SRAM的设计与实现[J].计算机应用与软件,2011,28(6):239-241,3.基金项目
宁波市自然科学基金项目(2006A610009). （2006A610009）
