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基于PLL+DDS接收机系统频率合成器的硬件实现

张福洪 马佳佳 张振强

电子器件2011,Vol.34Issue(3):292-298,7.
电子器件2011,Vol.34Issue(3):292-298,7.DOI:10.3969/j.issn.1005-9490.2011.03.014

基于PLL+DDS接收机系统频率合成器的硬件实现

Hardware Implementation of Receiver Syetem Frequency Synthesizer Based on DDS&PLL

张福洪 1马佳佳 1张振强1

作者信息

  • 1. 杭州电子科技大学通信工程学院,杭州310018
  • 折叠

摘要

Abstract

The paper takes the advantage of the PLL and DDS, using the PLL and DDS mixing method to design the hardware circuit of receiver system frenquency synthesizer. By the aid of EDA software ADS and ADISimPLL, some key modules are designed and simulated. Finally, the frequency synthesizer has been implemented with Cadence.Test results show that the frequency synthesizer achieves the design objective and the system has good performance.

关键词

PLL/DDS/频率合成器/硬件电路

Key words

PLL/ DDS/ frequency synthesizer/ hardware circuit

分类

信息技术与安全科学

引用本文复制引用

张福洪,马佳佳,张振强..基于PLL+DDS接收机系统频率合成器的硬件实现[J].电子器件,2011,34(3):292-298,7.

基金项目

浙江省新苗人才计划项目(ZX100701049) (ZX100701049)

电子器件

OA北大核心CSTPCD

1005-9490

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