电子器件2011，Vol.34Issue(3)：320-323,4.DOI:10.3969/j.issn.1005-9490.2011.03.020
基于SystemVerilog的网络处理器验证平台设计
Verification Platform's Design of Network Processor Based on SystemVerilog
摘要
Abstract
A verification platform's design of network processor based on systemverilog is presented in this paper.The platform is based on VMM, relational modules and the code of functional coverage are accomplished by SystemVerilog. Meanwhile, some SVA is inserted in designing code. When the network processor is running, from verification platform, the error can be discovered quickly and the verification of function can be achieved availably.关键词
网络处理器/VMM/验证平台/SustemVeriogKey words
network processor/ VMM/ verification platform/ SystemVerilog分类
信息技术与安全科学引用本文复制引用
刘萌,冯海洲,李康,马佩军,史江一..基于SystemVerilog的网络处理器验证平台设计[J].电子器件,2011,34(3):320-323,4.基金项目
高性能网络处理器设计与研究项目 （）
