电子器件2011，Vol.34Issue(3)：350-354,5.DOI:10.3969/j.issn.1005-9490.2011.03.027
一种可重构的通用总线接口验证平台的研究及实现
Research and Implementation of a Generic Reconfigurable Bus Interface-Based Verification Platform
刘芳 1谢峥 1连志斌 1王新安1
作者信息
- 1. 北京大学深圳研究生院集成微系统科学工程与应用重点实验室,广东深圳518055
- 折叠
摘要
Abstract
The bus interface UART was used as an example to introduce a high-performance verification platform.Based on System Verilog language, oriented towards the feedback of functional coverage, the platform generated test stimulus, and automatically checked the operating results. The platform has good features such as in reuse and efficiency. Practices showed that compared with the traditional verification platform, this platform has obvious advantages in terms of functional coverage and verifiable efficiency, and compared with VMM-based verification platform this platform shows its better features such as efficiency, flexibility, easy to learn and operating master.关键词
UART/SystemVerilog/带约束的随机方法/功能覆盖率/VMMKey words
UART/ SystemVerilog/ constrained random/ functional coverage/ VMM分类
信息技术与安全科学引用本文复制引用
刘芳,谢峥,连志斌,王新安..一种可重构的通用总线接口验证平台的研究及实现[J].电子器件,2011,34(3):350-354,5.
