液晶与显示2011，Vol.26Issue(3)：404-408,5.DOI:10.3788/YJYXS20112603.0404
二维提升小波的VLSI结构设计及FPGA验证
Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification
孟伟 1金龙旭 2韩双丽1
作者信息
- 1. 中国科学院长春光学精密机械与物理研究所,吉林长春130033
- 2. 中国科学院研究生院,北京100039
- 折叠
摘要
Abstract
In order to save the resource and improve the speed of wavelet transform's hardware realization, an effective 2-dimension wavelet transform hardware structure has been proposed.This structure used parallel pipeline architecture, each layer of wavelet transform processed by parallel while pixels processed by pipeline.And the structure can improve the speed of wavelet transform, save the on-chip and external memory resource.It had been tested on Xilinx SPARTEN-3 series FPGA by processing large image with size 1024×2048.Results showed the image processing speed could reach 80 Mpixel/s, meeting the real-time requirement.关键词
JPGA2000/小波变换/并行结构/提升算法Key words
JPGA2000/ wavelet transform/ parallel architecture/ lifting computation分类
信息技术与安全科学引用本文复制引用
孟伟,金龙旭,韩双丽..二维提升小波的VLSI结构设计及FPGA验证[J].液晶与显示,2011,26(3):404-408,5.
