计算机工程2011，Vol.37Issue(13)：20-25,6.DOI:10.3969/j.issn.1000-3428.2011.13.006
缓冲区结构效率分析
Efficiency Analysis of Buffer Structure
苏航 1薛彦涛2
作者信息
- 1. 兰州大学信息科学与工程学院,兰州,730000
- 2. 中国肮天二院研究生院,北京,100854
- 折叠
摘要
Abstract
To solve the problem of the data transmission speed mismatch between I/O device and CPU, this paper analyzes the efficiency of various buffer structure based on computer architecture. With Quartus Ⅱ which is Computer-Aided Design(CAD) using Electronic Design Automation(EDA) software, it designs the asynchronous dual-clock First In First Out(FIFO) buffer, including the buffer structure of the simulation,data recording, and analysis of its effectiveness. Analysis results show that the efficiency of computer system is closely related with that of FIFO. To improve the efficiency of computer system, the efficiency of FIFO is supposed to be improved first. At the same time, the improvement of the efficiency of FIFO is based on the improvement of the efficiency of computer system.关键词
异步FIFO/结构效率/EDA设计/亚稳态Key words
asynchronous First In First Out(FIFO)/ structure efficiency/ Electronic Design Automation(EDA) design/ metastable state分类
信息技术与安全科学引用本文复制引用
苏航,薛彦涛..缓冲区结构效率分析[J].计算机工程,2011,37(13):20-25,6.
