计算机工程2011，Vol.37Issue(13)：282-284,3.DOI:10.3969/j.issn.1000-3428.2011.13.093
FPGA实际可用性评估与发展趋势分析
Actual Usability Evaluation and Development Trend Anaysis of FPGA
摘要
Abstract
This paper introduces the development of Field Programmable Gate Array(FPGA), and evaluates the usability of FPGA devices which include the use of reconfigurable logic, Block RAM(BRAM), I/O resources, Digital Signal Processor(DSP) hard core, the selection of CPU soft core/hard core and the usable clock frequencies. It predicts future trend in the ever quest for high performance FPGA. It suggests not using slice resource more than 85％, selecting better supported tool company for soft/hard core and let all I/O signal buffered by registers.关键词
现场可编程门阵列/可用性评估/可重构逻辑/CPU软核/硬核/DSP固核Key words
Field Programmable Gate Array(FPGA)/ usability evaluation/ reconfigurable logic/ CPU soft core/hard core/ Digital Signal Processor (DSP) hard core分类
自科综合引用本文复制引用
俞吉波,孔雪,郑哲,祝永新,付宇卓..FPGA实际可用性评估与发展趋势分析[J].计算机工程,2011,37(13):282-284,3.基金项目
国家"863"计划基金资助重点项目(2009AA012201) （2009AA012201）
上海市国际科技合作基金资助项目(09540701900) （09540701900）
上海市科委重大科技攻关计划基金资助项目(08dz501600). （08dz501600）
