半导体学报2010，Vol.31Issue(6)：74-77,4.DOI:10.1088/1674-4926/31/6/064012
Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance
Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance
Dong Yaoqi 1Kong Weiran 2Nhan Do 3Wang Shiuh-Luen 2Lee Gabriel4
作者信息
- 1. Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences,Shanghai 200050,China
- 2. Grace Semiconductor Manufacturing Corporation,Shanghai 201203,China
- 3. Graduate University of the Chinese Academy of Sciences,Beijing 100049,China
- 4. Silicon Storage Technology Inc.,1171 Sonora Court,Sunnyvale,CA 94086,USA
- 折叠
摘要
关键词
split-gate flash/endurance/erase voltageKey words
split-gate flash/endurance/erase voltage引用本文复制引用
Dong Yaoqi,Kong Weiran,Nhan Do,Wang Shiuh-Luen,Lee Gabriel..Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance[J].半导体学报,2010,31(6):74-77,4.
