半导体学报2009，Vol.30Issue(10)：132-136,5.DOI:10.1088/1674-4926/30/10/105014
A multiple-pass ring oscillator based dual-loop phase-locked loop
A multiple-pass ring oscillator based dual-loop phase-locked loop
摘要
Abstract
A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of-99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.关键词
coarse-tuning/ dual-loop/ fine-tuning/ phase-locked loop/ phase noiseKey words
coarse-tuning/ dual-loop/ fine-tuning/ phase-locked loop/ phase noise分类
信息技术与安全科学引用本文复制引用
Chen Danfeng,Ren Junyan,Deng Jingjing,Li Wei,Li Ning..A multiple-pass ring oscillator based dual-loop phase-locked loop[J].半导体学报,2009,30(10):132-136,5.基金项目
Project supported by the National 11th Five-Year Plan of China (No. 51308020403), the Science and Technology Commission of Shanghai Municipality (No. 08706200700), and the National Hi-Tech Research and Development Program of China (No. 2009AA01Z261). （No. 51308020403）
