半导体学报2009，Vol.30Issue(10)：137-142,6.DOI:10.1088/1674-4926/30/10/105015
A novel noise optimization technique for inductively degenerated CMOS LNA
A novel noise optimization technique for inductively degenerated CMOS LNA
摘要
Abstract
This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.关键词
low noise/ optimization/ noise factorKey words
low noise/ optimization/ noise factor分类
信息技术与安全科学引用本文复制引用
Geng Zhiqing,Wang Haiyong,Wu Nanjian..A novel noise optimization technique for inductively degenerated CMOS LNA[J].半导体学报,2009,30(10):137-142,6.基金项目
Project supported by the National Natural Science Foundation of China (No. 90607007) and the State Key Development Program for Basic Research of China (Nos. 2006AA04A108, 2008AA010703). （No. 90607007）
