光通信技术2009，Vol.33Issue(11)：39-41,3.
高速专用GFP处理器的FPGA实现
Implementation in FPGA of the high speed and customization GFP processor
牛燚坤 1徐智勇 1乔庐峰 1陈德军2
作者信息
- 1. 解放军理工大学,通信工程学院,南京,210007
- 2. 中国人民解放军94860部队,南京,210047
- 折叠
摘要
Abstract
The paper use FPGA realized the GFP processor circuit which used to pack and unpack the nonstan-dard user data that will be transferred by SDH.The application of buffer manage made circuit can deal with the data of abrupt arrived and instantaneous high speed effectively.To adopt the parallel CRC arithmetic further improved the compute speed of GFP processor. The GFP processor realized in xilinx xc2vp2, which needs ap-proximately 700 4-input LUTs, and adopts 80MHz system clock,the width of data bus is 8,the capability of da-ta process can up to 640Mb/s.关键词
SDH/GFP/FPGA/并行CRCKey words
SDH/GFP/FPGA/parallel CRC分类
信息技术与安全科学引用本文复制引用
牛燚坤,徐智勇,乔庐峰,陈德军..高速专用GFP处理器的FPGA实现[J].光通信技术,2009,33(11):39-41,3.
