计算机工程与科学2009，Vol.31Issue(12)：110-112,123,4.DOI:10.3969/j.issn.1007-130X.2009.12.033
可配置并行BCH译码器的设计与实现
Design and Implementation of Configurable Parallet BCH Decoder
摘要
Abstract
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.The method includes how to enlarge the variable range of the configurable parameters,reduce the delay of decoding and achieve high data throughput.A BCH decoder for DVB-S2 is designed and implemented according to the method.关键词
可配置/并行/BCH译码器/DVB-S2Key words
configurable/parallel/BCH decoder/DVB-S2分类
信息技术与安全科学引用本文复制引用
陈旭灿,马宏强..可配置并行BCH译码器的设计与实现[J].计算机工程与科学,2009,31(12):110-112,123,4.基金项目
国家863计划资助项目(2007AA01Z287) （2007AA01Z287）
