计算机工程与科学2009，Vol.31Issue(z1)：64-67,4.DOI:10.3969/j.issn.1007-130X.2009.A1.020
基于FPGA的细粒度并行K-means算法加速器的设计与实现
Fine-Grained Parallel K-means Clustering Algorithm on FPGA
摘要
Abstract
We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA. We partition tasks by rows and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load data from external memory. To our knowledge, our implementation with 4 PEs is the only FPGA accelerator(XC5VLX330) implementing the complete K-means clustering algorithm. The experimental results show a factor of more than 15 speedup over the Cluster 3.0 software running on a PC platform with Pentium 4 2.66GHz CPU.关键词
K-means算法/FPGA/硬件加速器/浮点实现Key words
K-means algorithm/ FPGA/ hardware accelerator/ float point/分类
信息技术与安全科学引用本文复制引用
倪时策,窦勇,雷元武,赵建勋..基于FPGA的细粒度并行K-means算法加速器的设计与实现[J].计算机工程与科学,2009,31(z1):64-67,4.基金项目
国家自然科学基金资助项目(2007AA01Z106) （2007AA01Z106）
