数据采集与处理2009，Vol.24Issue(z1)：177-181,5.
一种宽带高性能TIADC时钟发生器
Design and Implementation of Wideband High-Performance TIADC Clock Generator
摘要
Abstract
To solve the clock limitations of time-interleaved analog-to-digital converter (TIADC),a solution of wideband high-performance TIADC clock generator is proposed.The clock distributor and the programmable delayer are used to transfer the global clock into multichannel clocks and set multiphase clocks for each sub-ADCs accordingly.Furthermore,a configurable clock source and the ECL propagation logic with ECL-CMOS transfer circuits are designed to output both ECL and CMOS clock with low jitter for the sub-ADCs of TIADC system.The example design is used in a 4 channel 12 bit 320 M sampling per second TIADC system.Experimental results indicate that the designed clock generator can generate the CMOS/ECL clocks for the TIADC system with 10 ps time-skew mismatch and the clock jitter is smaller 2 ps at 80 MHz.关键词
时钟树/TIADC系统/时钟发生器/时间失配/低抖动Key words
clock tree/TIADC system/clock generator/time mismatch/low clock jitter分类
信息技术与安全科学引用本文复制引用
朱志东,邹月娴,陶阁..一种宽带高性能TIADC时钟发生器[J].数据采集与处理,2009,24(z1):177-181,5.基金项目
国家自然科学基金(60775003)资助项目. （60775003）
