半导体学报2011，Vol.32Issue(7)：62-69,8.DOI:10.1088/1674-4926/32/7/075001
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifierfor an IR-UWB receiver
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifierfor an IR-UWB receiver
摘要
Abstract
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier (THA) in 0.13 μm CMOS for an impulse radio ultra-wideband (IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm2.The ADC achieves a figure of merit of 3.75 p J/conversion-step.关键词
flash ADC/sub-sampling/track and hold amplifier/resistive averaging technique/comparator/IRUWBKey words
flash ADC/sub-sampling/track and hold amplifier/resistive averaging technique/comparator/IRUWB引用本文复制引用
Zhao Yi,Wang Shenjie,Qin Yajie,Hong Zhiliang..A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifierfor an IR-UWB receiver[J].半导体学报,2011,32(7):62-69,8.基金项目
Project supported by the National High Technology Research and Development Program of China (No.2009AA01 Z261) and the State Key Laboratory of Wireless Telecommunication,Southeast University. （No.2009AA01 Z261）
