半导体学报2011，Vol.32Issue(7)：131-135,5.DOI:10.1088/1674-4926/32/7/075011
A novel high reliability CMOS SRAM cell
A novel high reliability CMOS SRAM cell
Xie Chengmin 1Wang Zhongfang 1Wu Longsheng 1Liu Youbao1
作者信息
- 1. Computer Research & Design Department, Xi'an Microelectronic Technique Institutes, Xi'an 710054, China
- 折叠
摘要
Abstract
A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed.By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell.So the hold,read SNM and critical charge increase greatly.The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors.The hold and read SNM of the new cell increase by 72% and 141.7%,respectively,compared to the 6T design,but it has a 54% area overhead and read performance penalty.According to these features,this novel cell suits high reliability applications,such as aerospace and military.关键词
single-event-upset/static noise margin/critical charge/SRAMKey words
single-event-upset/static noise margin/critical charge/SRAM引用本文复制引用
Xie Chengmin,Wang Zhongfang,Wu Longsheng,Liu Youbao..A novel high reliability CMOS SRAM cell[J].半导体学报,2011,32(7):131-135,5.
