计算机应用研究2011，Vol.28Issue(8)：2964-2966,2996,4.DOI:10.3969/j.issn.1001-3695.2011.08.045
基于预测缓存的低功耗TLB快速访问机制
Fast and low power TLB access mechanism with prediction buffer
摘要
Abstract
This paper proposed a fast and low power TLB access mechanism with prediction buffer based on memory access locality principle, and designed a two-level TLB structure implemented by SARM instead of CAM to achieve fast access of the full associated TLB. Between the two levels of the introduced TLB, an independent and hardware configurable prediction buffer was designed to dynamically predict the access sequences of the second level TLB, which could reduce its access penalty when the first level TLB missed and significantly reduce the dynamic power consumption with little control logic. Experiment shows that compared with the traditional two-level TLB structure, the average access cycles of the second level TLB are about 20% of the traditional one, with only 1.81% area increment, which support low power and low cost embedded application.关键词
内存管理单元/两级转换旁置缓冲器/内容寻址存储器/静态随机存储器/预测缓存/快速访问/低功耗Key words
MMU/ two-level TLB/ CAM/ SRAM/ prediction buffer/ fast access/ low-power分类
信息技术与安全科学引用本文复制引用
武淑丽,孟建熠,王荣华,严晓浪,葛海通..基于预测缓存的低功耗TLB快速访问机制[J].计算机应用研究,2011,28(8):2964-2966,2996,4.基金项目
国家“863”高科技研究发展计划资助项目(2004AA1 Z1020) （2004AA1 Z1020）
