现代电子技术2011，Vol.34Issue(20)：181-183,3.
USB3.0中五分频电路设计
Design for Circuit of 5 Frequency Divider in USB3.0
赵光 1宫玉彬1
作者信息
- 1. 电子科技大学物理电子学院,四川成都610054
- 折叠
摘要
Abstract
A new divided-by-5 frequency divider based on current mode logic (CML) and true single phase clock (TSPC) are designed and implemented by using 65 nm CMOS process technology. The divider is applied to the clock frequency conversion in physical layer of USB3. 0, and the output signal has a 50% duty cycle. Simulation result show the divider based on CML can work in 8 GHz frequency steadily and it's power dissipation is 1. 9 mW; the divider based on TSPC can work in 10 GHz frequency steadily and ifs power dissipation is 0. 2 mW. Both dividers can satisfy the standard of USB3. 0.关键词
分频器/触发器/电流模式逻辑/单相位时钟逻辑Key words
frequency divider/ trigger/ current mode logic (CML)/ logic of single phase clock (TSPC)分类
信息技术与安全科学引用本文复制引用
赵光,宫玉彬..USB3.0中五分频电路设计[J].现代电子技术,2011,34(20):181-183,3.
