半导体学报2011，Vol.32Issue(8)：40-45,6.DOI:10.1088/1674-4926/32/8/084002
Gate-enclosed NMOS transistors
Gate-enclosed NMOS transistors
Fan Xue 1Li Ping 1Li Wei 1Zhang Bin 1Xie Xiaodong 1Wang Gang 1Hu Bin 1Zhai Yahong1
作者信息
- 1. School of Microelectronics and Solid-State Electronics, State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China, Chengdu 610054, China
- 折叠
摘要
Abstract
In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process.By comparing the minimum W/L ratios and transistor areas,it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed.Furthermore,by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio,it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%.It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors,since it is targeted only toward the two-edged transistor.A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.关键词
radiation/ total ionizing dose/ gate-enclosed transistor/ annular NMOS/ ring NMOSKey words
radiation/ total ionizing dose/ gate-enclosed transistor/ annular NMOS/ ring NMOS引用本文复制引用
Fan Xue,Li Ping,Li Wei,Zhang Bin,Xie Xiaodong,Wang Gang,Hu Bin,Zhai Yahong..Gate-enclosed NMOS transistors[J].半导体学报,2011,32(8):40-45,6.
