计算机工程2011，Vol.37Issue(20)：133-135,3.DOI:10.3969/j.issn.1000-3428.2011.20.046
一种高性能低功耗的密码SoC平台
High-performance and Low-power Dissipation Cipher SoC Platform
摘要
Abstract
A cipher System on a Chip(SoC) platform is designed against the lack of applicability of current cipher SoC platform. Special-designed cipher coprocessor is integrated to realize several cryptographic algorithms and power reduction of the platform is reduced by adaptive clock gate control unit in system level. Several high and low speed communication interfaces are also supplied to complete external data exchange. Experimental results show that the platform can support different cipher operations effectively with lower power dissipation and higher data throughput.关键词
片上系统/密码协处理器单元/自适应时钟门控单元/通信接口/现场可编程门阵列Key words
System on a Chip(SoC)/ cipher coprocessor unit/ adaptive clock gate control unit/ communication interface/ Field Programmable Gate Array(FPGA)分类
自科综合引用本文复制引用
程建雷,戴紫彬,徐金甫..一种高性能低功耗的密码SoC平台[J].计算机工程,2011,37(20):133-135,3.基金项目
国家“863”计划基金资助项目(2008AA01Z 103) （2008AA01Z 103）
