计算机工程2011，Vol.37Issue(20)：252-254,267,4.DOI:10.3969/j.issn.1000-3428.2011.20.086
一种SEU硬核检测电路的设计与实现
Design and Implementation of SEU Hard Core Detection Circuit
摘要
Abstract
Current Field Programmable Gate Array(FPGA) chip can only be erased and configured periodically and repeatedly during the Single Event Upset(SEU) error detection, and this is not a continuous error detection and correction method. Aiming at this problem, this paper presents a continuous SEU hard core detection circuit with real-time error detection information output for external circuits. The circuit improves the traditional FPGA frame storage structureca and can work continuously for read-back Cyclic Redundancy Check(CRC) without affecting the normal state of FPGA. The design has been used in FDP3P7 FPGA chip which is designed independently. Test results indicate that the SEU hard core detection circuit can work continuously on the configuration bit-stream read-back CRC in the SO MHz frequency and real-time error detection information output correctly.关键词
现场可编程门阵列/单粒子翻转/循环冗余校验/SEU检测/片上可编程系统Key words
Field Programmable Gate Array(FPGA)/ Single Event Upset(SEU)/ Cyclic Redundancy Check(CRC)/ SEU detection/ System on a Programmable Chip(SOPC)分类
信息技术与安全科学引用本文复制引用
崔鹏,陈利光,来金梅,周灏,鲍丽春..一种SEU硬核检测电路的设计与实现[J].计算机工程,2011,37(20):252-254,267,4.基金项目
国家“863”计划基金资助项目(2007AA01 Z285) （2007AA01 Z285）
国家自然科学基金资助项目(60876015) （60876015）
上海市科技创新行动计划基金资助项目“国产自主知识产权FPGA的产业化应用和深入研发”(08706200101) （08706200101）
