现代电子技术2011，Vol.34Issue(19)：183-186,4.
基于CPLD的简易数字频率计的设计
Design of Simple Digital Frequency Meter Based on CPLD
摘要
Abstract
The component of CPLD provided enormous convenience and flexibility for the modern electronic design, which changed the complicated digital electronic system design into chip design and performed the online modification for the design conveniently. The frequency measurement principle of the frequency meter is introduced, the method of using CPLD to count the frequency of the signal for completing the design of the simple digital frequency meter is proposed. The frequency meter used the VHDL-based "Top-Down" design method, set out the total requirement of system, refined the design content by "Top-Down" method and achieved the design of hardware finally. The designed circuit was simulated, programmed on the aim device and ran on series SoPC /EDA experiment chest. The design can meet the requirement of the practical frequency measurement.关键词
CPLD/VHDL/频率计/设计Key words
CPLD/ VHDL/ frequency meter/ design分类
信息技术与安全科学引用本文复制引用
张洋..基于CPLD的简易数字频率计的设计[J].现代电子技术,2011,34(19):183-186,4.
