一种基于类分数分频的△∑延时锁定环的设计OACSTPCD
Design of ΔΣ Delay Lock Ring Based on Class Score Points Frequency
针对现有△∑延时锁定环中调制器的功耗问题,提出一种基于类分数分频的△∑延时锁定环的设计方法.通过使用分频器,降低△∑延时锁定环中调制器、电荷泵、相位选择器等模块的工作频率,由此减小设计难度,并解决了传统结构中的调制器功耗和相位切换的毛刺问题.同时采用自参考多相时钟和FIR噪声滤除技术解决了使用分频器造成的相位模糊以及量化噪声的恶化问题.测试结果表明,该结构可以在基于低频△∑调制中实现低于1ps的时域分辨率,并且获得与传统结构相当的时钟抖动性能.
According to the power consumption problem existing in ΔΣ delay locking ring modulator, a design method of class score points frequency ΔΣ delay locking ring is proposed.Through the use of separate frequency device, the working frequency of the ΔΣ delay locking ring modulator, charge pump and phase selector module is reduced, thus the difficulty of the design is decreased, and the traditional structure of the power and phase transition modulator deburring pr…查看全部>>
易鸿
四川文理学院物理与工程技术系,四川 达州 635000
信息技术与安全科学
类分数锁相环延时锁定环△∑调制
class scorephase-locked loop delay-locked ringΔΣ modulation
《西华大学学报（自然科学版）》 2011 (5)
57-60,68,5
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