计算机科学与探索2011，Vol.38Issue(10)：1-5,12,6.
片上网络互连拓扑综述
Survey on the Networks-on-Chip Interconnection Topologies
摘要
Abstract
Along with the development of device, process and application technology, chip multiprocessor is becoming the mainstream technology. As the scale of chip multiprocessor as well as the number of integrated on-chip cores is getting larger and larger, the network-on-chip, which is dedicated to the interconnection and communication among on-chip cores and other components, is becoming one of the performance bottlenecks of chip multiprocessor. The topology of network-on-chip defines the physical layouts and the interconnection patterns of network nodes,determines the cost,latency, throughput, area, fault tolerance and power of network-on-chip,and impacts on the network routing policies, the placement and routing designs of network chips. Therefore, the topology is one of the key technologies of network-orr chips. The paper compared various topological structures of network-on-chips in brief,analyzed their performances,and proposed recommendations for future research on the topology of network-on-chip.关键词
片上多处理器/片上网络/拓扑/性能分析Key words
Chip multiprocessor, Network-on-chip, Topology, Performance analysis分类
信息技术与安全科学引用本文复制引用
王炜,乔林,汤志忠..片上网络互连拓扑综述[J].计算机科学与探索,2011,38(10):1-5,12,6.基金项目
本文受国家自然科学基金项目(60773149,61073007),国家高技术研究发展计划(863)项目(2006AA01A101,2008AA01Z108),国家重点基础研究发展计划(973)项目(2007CB310900)资助. （60773149,61073007）
