东南大学学报（自然科学版）2011，Vol.41Issue(6)：1132-1136,5.DOI:10.3969/j.issn.1001-0505.2011.06.003
JPEG2000全并行位平面编码器的VLSI设计验证
Design and verification of the parallel architecture of the bit plane coder in JPEG2000
摘要
Abstract
The algorithm and parallel architecture of the bit plane coder (BPC) in joint photographic experts group 2000 (JPEG2000) is studied. The data dependence in the coding passes is analyzed with a column regarded as the basic data unit. It's discovered that when the significance states of a former column are cached, and the original coefficients of the current column and the next two columns are ready, the parallel coding in one coding window between passes and bit planes is possible. After that, the loop-coding can be realized with a new column read in each time. Based on this conclusion , the parallel architecture with a 3 stages pipeline is designed, which can process 32 x 32 wavelet sub-band within 259 cycles and keep a low hardware cost. The synthesis results on FPGA (field programmable gate array) show that the system frequency can reach 76. 355 MHz, and the throughput is 301. 9Mcoefficient/sec. The real-time image-process can be satisfied.关键词
JPEG2000/位平面编码/通道并行/位平面并行/VLSIKey words
JPEG2000 (joint photographic experts group 2000)/BPC (bit plane coder) /pass parallel/bit plane parallel/VLSI (very large scale integration)分类
信息技术与安全科学引用本文复制引用
刘文松,朱恩,王健,徐龙涛,黄宁..JPEG2000全并行位平面编码器的VLSI设计验证[J].东南大学学报（自然科学版）,2011,41(6):1132-1136,5.基金项目
国家高技术研究发展计划(863计划)资助项目(2009AA11Z219). （863计划）
