电子学报2011，Vol.39Issue(11)：2473-2479,7.
一种面向超标量处理器的高能效指令缓存路选择技术
An Energy-Efficient Combining Way Selective Technique for the Instruction Cache in Superscalar Microprocessors
摘要
Abstract
Way selective technique could reduce the instruction cache energy consumption significantly. However, existing solutions usually bring extra fetch latency due to mispredictions or complicated updating mechanism,reducing the energy-efficiency. The paper presents an energy-efficient Combining Way Selective Cache for the instruction cache in superscalar processors (CWS-Cache). It combines the advantages of way prediction and way history techniques, and selects the best way selective mechanism for different situations. It not only reduces the instruction fetch energy effectively,but also improves performance by reducing the latency of misalignment fetch groups. Experimental results demonstrate that, on average, CWS-Cache reduces fetch energy consumption of the 8-way set-associative instruction cache in the baseline processor by 84.98% ,and improves performance by 3.5% .Compared with three existing techniques,CWS-Cache improves the energy-delay product (EDP) by 15.48% , 14.13% , and 8.76% .respectively.关键词
超标量处理器/路预测/路历史Key words
superscalar microprocessors/ way prediction/ way history分类
信息技术与安全科学引用本文复制引用
谢子超,陆俊林,佟冬,王箫音,程旭..一种面向超标量处理器的高能效指令缓存路选择技术[J].电子学报,2011,39(11):2473-2479,7.基金项目
国家"核高基"重大专项:安全适用计算机CPU研发与应用项目(No.2009ZX01029-001-002) （No.2009ZX01029-001-002）
