电子学报2011，Vol.39Issue(11)：2486-2491,6.
JPEG2000算术编码器的算法优化和VLSI设计
Optimization Algorithm and VLSI Design of the Arithmetic Coder in JPEG2000
摘要
Abstract
The algorithm and the hardware implementation of Arithmetic Coder (AC) in JPEG2000 are studied. A new kind of the sequence structure of the Renormalization Procedure (RP) is proposed. With the independent total-shift prediction procedure added,the current context can be processed serially by AC without loop computation.Based on the proposed algorithm, the 3-stage pipeline architecture with a slave pipeline is designed, where the pipeline is used to process the common situation of no byte-output and the slave pipeline is used to detect and process the byte-output situation separately, in order to reduce the critical path of the sub circuits.The synthesis result by the technology library of TSMC 0.18μm shows that the system clock frequency is 578MHz and the throughput is about 520 Msymbols/s.Comparing with the published works by the same technology library at home and abroad,they are optimized by 40% and 26% at least respectively.关键词
JPEG2000/算术编码/重归一化规程/流水线结构Key words
JPEG2000/ AC/ renormalization procedure/ pipeline architecture分类
信息技术与安全科学引用本文复制引用
刘文松,朱恩,王健,徐龙涛,林叶..JPEG2000算术编码器的算法优化和VLSI设计[J].电子学报,2011,39(11):2486-2491,6.基金项目
863计划资助项目(No.2009AA11Z219) （No.2009AA11Z219）
