西安工程大学学报2011，Vol.25Issue(4)：555-559,5.
一种基于FPGA的3DES加密算法实现
3DES implementation based on FPGA
任芳 1杨承睿 1陈雷华1
作者信息
- 1. 陕西省气象科技服务中心,陕西西安 710014
- 折叠
摘要
Abstract
In order to meet the demand of plenty continuous encrypting-deciphering, and meet the demand of enhancing the security of encrypting-deciphering algorithm, the fundamental technologies such as pipeline technology and finite state machine (FSM) are applied, 3DES encryption algorithm's encryption chip's circuit based on FPGA are designed and realized. On the platform of FPGA of Xilinx Virtex4 series, the ISE 10. 1 development kits is used to realize the simulation confirmation and the logic synthesis. The result indicates that the 3DES cryptographic system's speed is able to achieve 860.660Mbps, and the encrypting-deciphering speed is greatly enhanced. The design could be used in network security products and other security equipment extensively.关键词
FPGA:3DES算法/VHDL/有限状态机:流水线技术Key words
3DES/FPGA/VHDL/state machine/pipeline technology分类
信息技术与安全科学引用本文复制引用
任芳,杨承睿,陈雷华..一种基于FPGA的3DES加密算法实现[J].西安工程大学学报,2011,25(4):555-559,5.
