半导体学报2011，Vol.32Issue(3)：100-104,5.DOI:10.1088/1674-4926/32/3/035004
A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology
A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology
摘要
Abstract
This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.关键词
phase-locked loop/ VCO/ charge pump/ current mismatchKey words
phase-locked loop/ VCO/ charge pump/ current mismatch引用本文复制引用
Mei Niansong,Sun Yu,Lu Bo,Pan Yaohua,Huang Yumei,Hong Zhiliang..A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology[J].半导体学报,2011,32(3):100-104,5.基金项目
Project supported by the National High Technology Research and Development Program of China (No.2009AA011605). （No.2009AA011605）
