A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technologyOACSCDCSTPCDEI
A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology
This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter i…查看全部>>
Mei Niansong;Sun Yu;Lu Bo;Pan Yaohua;Huang Yumei;Hong Zhiliang
State Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, ChinaState Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, ChinaState Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, ChinaState Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, ChinaState Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, ChinaState Key Laboratory of ASIC & Systems, Fudan University, Shanghai 201203, China
phase-locked loop VCO charge pump current mismatch
phase-locked loop VCO charge pump current mismatch
《半导体学报》 2011 (3)
100-104,5
Project supported by the National High Technology Research and Development Program of China (No.2009AA011605).
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