半导体学报2011，Vol.32Issue(11)：162-166,5.DOI:10.1088/1674-4926/32/11/115017
Novel SEU hardened PD SOI SRAM cell
Novel SEU hardened PD SOI SRAM cell
Xie Chengmin 1Wang Zhongfang 1Wang Xihu 1Wu Longsheng 1Liu Youbao1
作者信息
- 1. Computer Research & Design Department, Xi'an Microelectronic Technique Institutes, Xi'an 710054, China
- 折叠
摘要
Abstract
A novel SEU hardened 10T PD SOI SRAM cell is proposed.By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors,this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOl transistor which causes the SEU in PD SOI SRAM.Mixed-mode simulation shows that this novel cell completely solves the SEU,where the ion affects the single transistor.Through analysis of the upset mechanism of this novel cell,SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references.To achieve this,the new cell adds four transistors and has a 43.4% area overhead and performance penalty.关键词
SEU/ PD SOI SRAM/ parasitic BJT/ mixed-mode simulationKey words
SEU/ PD SOI SRAM/ parasitic BJT/ mixed-mode simulation引用本文复制引用
Xie Chengmin,Wang Zhongfang,Wang Xihu,Wu Longsheng,Liu Youbao..Novel SEU hardened PD SOI SRAM cell[J].半导体学报,2011,32(11):162-166,5.
