半导体学报2012，Vol.33Issue(1)：59-63,5.DOI:10.1088/1674-4926/33/1/014005
Impact of parasitic resistance on the ESD robustness of high-voltage devices
Impact of parasitic resistance on the ESD robustness of high-voltage devices
摘要
Abstract
The impacts ofsubstrate parasitic resistance and drain ballast resistance on electrostatic discharge (ESD)robustness of LDMOS are analyzed.By increasing the two parasitic resistances,the ESD robustness of LDMOS are significantly improved.The proposed structures have been successfully verified in a 0.35 μm BCD process without using additional process steps.Experimental results show that the second breakdown current of the optimal structure increases to 3.5 A,which is about 367% of the original device.关键词
electrostatic discharge/high-voltage device/LDMOS/parasitic resistanceKey words
electrostatic discharge/high-voltage device/LDMOS/parasitic resistance引用本文复制引用
Lin Lijuan,Jiang Lingli,Fan Hang,Zhang Bo..Impact of parasitic resistance on the ESD robustness of high-voltage devices[J].半导体学报,2012,33(1):59-63,5.基金项目
Project supported by the National Natural Science Foundation of China (No.60906038). （No.60906038）
