半导体学报2012，Vol.33Issue(2)：1-9,9.DOI:10.1088/1674-4926/33/2/021001
MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance
MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance
摘要
Abstract
Low-frequency and High-frequency Capacitance-Voltage (C-V) curves of Silicon Metal-Oxide-Semiconductor Capacitors,showing electron and hole trapping at shallow-level dopant and deep-level generationrecombination-trapping impurities,are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs,in contrast to chemical means via impurity characteristics previously reported.Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals.Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.关键词
MOS/ silicon/ trapping capacitance/ dopant impurities/ donors/ acceptorsKey words
MOS/ silicon/ trapping capacitance/ dopant impurities/ donors/ acceptors引用本文复制引用
揭斌斌,薩支唐..MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance[J].半导体学报,2012,33(2):1-9,9.基金项目
This investigation is supported by the Xiamen University,China,and the CTSAH Associates (CTSA),founded by the late Linda Su-Nan Chang Sah. （CTSA）
