重庆邮电大学学报（自然科学版）2012，Vol.24Issue(1)：60-63,95,5.DOI:10.3979/j.issn.1673-825X.2012.01.012
引入SRAM的三级缓存技术在高速通信中的应用
Tri-stage buffer used in the high-speed communication by the addition of SRAM
摘要
Abstract
In the high-speed communication,data process system usually needs data buffer to store data timely. The FIFO which is structured by using the internal resources of field programmable gate array (FPGA) has limited capacity, which easily leads to the overflow of FIFO and data discarded, if the speed of reading does not match the speed of writing. To resolve this problem,this paper designs and realizes tri-stage buffer. A SRAM whose capacity is 1MB is added to the exterior of FPGA as the middle buffer. The input buffer and output buffer are the FIFO of FPGA, and FPGA controls the data transmission and the writing and reading operation of the SRAM. Adopting tri-stage buffer technique simplifys the complexity of the hardware and increases the reachability of the design. Tests show that tri-stage buffer technique is reliable and steady.关键词
三级缓存/静态随机存储器/先进先出(FIFO)/现场可编程门阵列(FPGA)Key words
tri-stage buffer, static random access memory(SRAM) .first in first out(FIFO) ,field programmable gate array (FPGA)分类
信息技术与安全科学引用本文复制引用
史赟,郑永秋,任勇峰..引入SRAM的三级缓存技术在高速通信中的应用[J].重庆邮电大学学报（自然科学版）,2012,24(1):60-63,95,5.基金项目
国家自然科学基金(60871041) （60871041）
