电子科技2011，Vol.24Issue(12)：35-37,3.
基于SystemVerilog的I^2C总线模块验证
Verification of I^2C Bus Model Using SystemVerilog
摘要
Abstract
A design for IP verification of I2C bus module based on Systemverilog is introduced.The verification design based on the object-oriented method can be easily reused.The structure of Systemverilog is analyzed and I2C bus protocol is introduced.After that,the paper focuses on the design of the affair generator and drive in the verification environment关键词
Systemverilog/I^2C总线/事务产生器/事务驱动器Key words
systemverilog/I^2 C bus/generation/drive分类
信息技术与安全科学引用本文复制引用
闫涛,申志飞,易茂祥,梅春雷..基于SystemVerilog的I^2C总线模块验证[J].电子科技,2011,24(12):35-37,3.基金项目
安徽省教育厅自然科学重点基金资助项目 （）
