电子科技2012，Vol.25Issue(1)：65-68,4.
基于FPGA的SDX总线与Wishbone总线接口设计
The Design of SDX-bus and Wishbone-Bus Interface Based on FPGA
刘娟 1张智鹏1
作者信息
- 1. 西安电子科技大学电子工程学院,陕西西安710071
- 折叠
摘要
Abstract
Aiming at the requirement of reliability, high data management efficiency as well as hardware cost of the airborne information acquisition system, this article mainly introduces the interface conversion of Sdx-bus and Wishbone-bus. The implementation of the design is based on Verilog HDL Language. It is simulated on the Model- Sim software, synthesized on the Quartus platform and tested through FPGA from The Cyclone Ⅲ by Ahera company. The results show that the design is feasible.关键词
Verilog/HDL/SDX总线/Wishbone总线/Modelsim/Quartus/ⅡKey words
Verilog HDL/SDX-bus/Wishbone-bus/Modelsim/Quartus Ⅱ分类
信息技术与安全科学引用本文复制引用
刘娟,张智鹏..基于FPGA的SDX总线与Wishbone总线接口设计[J].电子科技,2012,25(1):65-68,4.
