电子科技大学学报2011，Vol.40Issue(6)：898-904,7.DOI:10.3969/j.issn.1001-0548.2011.06.018
层次化互连结构的EVMPSoC设计与实现
Design and Implementation of Embedded Visual Media Process SoC with Hierarchy on-Chip Bus Architecture
摘要
Abstract
In order to meet the high demand of computation intensive and band-width exhausting media applications for embedded system, a heterogeneous multi-core embedded visual media processor, named EVMPSoC, is proposed. The chip consists of a main processor called EPStar3, which is a 32 bit RISC embedded processor, and two SIMD coprocessor, which are designed by application-specific instruction set. According to the communication characteristics of media applications, the hierachy high/low speed bus and dual band-width parallel memory access with multi-channel are used as the on-chip bus Architecture of EVMPSoC. The chip was taped out sucessful using SMIC 0.13 jim LVT CMOS technology and packaged by Amkor with PBGA 400. It runs well at peak frequency 416 MHz, and shows its high efficiency and avaliability.关键词
嵌入式可视媒体处理/层次化高低速系统总线/多通道访存/多核SoCKey words
embedded visual media process/ hierachy high/low speed system bus/ memory access with multi-channel/ multicore SoC分类
信息技术与安全科学引用本文复制引用
沈剑良,严明,李思昆,刘磊..层次化互连结构的EVMPSoC设计与实现[J].电子科技大学学报,2011,40(6):898-904,7.基金项目
国家自然科学基金(90707003,61076020) （90707003,61076020）
