福州大学学报（自然科学版）2011，Vol.39Issue(6)：857-861,5.DOI:35-1117/N.20111220.0955.022
带I2C接口的时钟IP核设计与优化
The design and optimization of a clock IP core with I2C interface
摘要
Abstract
In this paper, FPGA programmable logic devices and hardware description language Verilog were used to implement an IP core with the fuctions such as data transmission, time adjustment, and alarm clock. On that basis, methods of functional simulation and optimization of the IP core were analyzed and discussed, and the feasibility of this design was demonstrated by simulation, synthesize, and optimization through simulating tools modelsim and logic synthesis optimization tools Design Compile.关键词
FPGA/Verilog/时钟/仿真/优化Key words
FPGA/ Verilog/ clock/ simulation/ optimization分类
信息技术与安全科学引用本文复制引用
邱枫,杨尊先..带I2C接口的时钟IP核设计与优化[J].福州大学学报（自然科学版）,2011,39(6):857-861,5.基金项目
福建省自然科学基金资助项目(2010J01332) （2010J01332）
教育部出国留学人员回国启动基金资助项目(LXKQ201101) （LXKQ201101）
