福州大学学报（自然科学版）2011，Vol.39Issue(6)：862-867,6.DOI:35-1117/N.20111220.1002.027
高性能64位并行前缀加法器全定制设计
Full - custom design of high - performance 64 - bit Parall - Prefix adder
摘要
Abstract
A parall - prefix adder based on 64 - bit radix - 4 Kogge - Stone tree algorithm principle is proposed in this paper. The architecture is optimized using domino dynamic logic, clock delayed domino and transmission pipes logic, which reduces the gate delay of each stage in the adder dramatically. In order to achieve small layout area and good performance, heuristic Euler algorithm is adopted to determine the block carry generation signals circuit structure, multi - output domino logic is adopted to optimize the block carry propagate signals, and six transmission pipes logic is used to build a half - adder. Using SMIC 0.18 μm 1P4M CMOS process for layout design, the adder's area is 0.137 9mm2. In the worst case, the computation time is 532.26 ps.关键词
并行前缀加法器/基4点操作/多米诺逻辑/欧拉路径算法Key words
parall - prefix adder/ radix - 4 dot operation/ dynamic logic/ Euler algorithm/ stick figure分类
信息技术与安全科学引用本文复制引用
王仁平,何明华,魏榕山,陈传东,戴惠明..高性能64位并行前缀加法器全定制设计[J].福州大学学报（自然科学版）,2011,39(6):862-867,6.基金项目
福建省科技重大专项基金资助项目(2009HZ010002) （2009HZ010002）
福建省教育厅科研资助项目(JA09001) （JA09001）
福建省自然科学基金资助项目(2009J05143) （2009J05143）
