航空兵器Issue(5)：56-61,6.
一种可扩展的并行处理器模型设计及性能评估
An Extensible Parallel Processor Simulator Design and Evaluation
摘要
Abstract
Adopting the parallel processor to process image in parallel is an effective way to improve the processing rate. In this paper, an extensible parallel processor for image processing （EPIP） and spe- cific instruction sets are proposed, based on the analysis of recent international and national progress of parallel processors. Many stream processor units （SP） are reused in the developed processor, which are organized in the single instruction multiple data （SIMD） way to fully exploit the data-level parallel. The very long instruction word （VLIW） and simultaneous muhithreading （SMT） technologies are implemented in a single SP, which realizes the instruction-level parallel （ILP） and task-level parallel （TLP） respec- tively. Specific instruction sets support the hybrid addressing of private registers and shared registers. The SystemVerilog is employed to build up the cycle-based simulation model of the proposed architecture, and several common image processing algorithms are mapped to the simulator. Finally, the preliminary per- fonnance of EPIP is given.关键词
并行处理器/图像处理/微体系结构/SystemVerilog/仿真模型Key words
parallel processor/image processing/micro-architecture/SystemVerilog/simulationmodel分类
信息技术与安全科学引用本文复制引用
陈鹏,袁雅婧,桑红石,张天序..一种可扩展的并行处理器模型设计及性能评估[J].航空兵器,2011,(5):56-61,6.基金项目
航空科学基金资助项目 （）
