计算机工程2011，Vol.37Issue(23)：223-225,3.
基于SystemVerilog的NoC测试平台
NoC Testbench Based on SystemVerilog
摘要
Abstract
For solving the low efficiency of Network on Chip(NoC) verification, this paper constructs the coverage-driven constrained random and hierarchical NoC testbench based on the Verification Methodology Manual(VMM) and application of SystemVerilog. Results of NoC performance evaluation with heterogeneous topologies or traffic distributions show that the testbench is superior in generality, has good adaptability, scalability , and can effectively improves the verification efficiency.关键词
SystemVerilog语言/片上网络/验证方法学/测试平台/功能覆盖率Key words
System Verilog language/ Network on Chip(NoC)/ Verification Methodology Manual(VMM)/ testbench/ functional coverage rate分类
信息技术与安全科学引用本文复制引用
柯夏志,张颖..基于SystemVerilog的NoC测试平台[J].计算机工程,2011,37(23):223-225,3.基金项目
南京航空航天大学基本科研业务费专项科研基金资助项目 (NS2010115) （NS2010115）
