计算机工程2012，Vol.38Issue(1)：233-235,3.DOI:10.3969/j.issn.1000-3428.2012.01.076
基于Radix-4Booth编码的乘法器优化设计
Optimal Design of Multiplier Based on Radix-4 Booth Encoding
摘要
Abstract
The traditional Radix-4 Booth encoding will produce the complement computing operation emerged in the process of negative partial product generation, which influences the word efficiency for multiplier. Aiming at this problem, this paper puts forward a multiplier optimal design of recombining partial products. By adding an "or" gate operation and simple hard-wired recombinant, it avoids addition operation in the complement computing process, and does not generate redundant partial product. The validated result on 32-bit multiplier shows that the design can effectively reduce the critical path delay and chip area consumption.关键词
Radix-4 Booth编码/乘法器/部分积/关键路径延迟/芯片面积消耗Key words
Radix-4 Booth encoding/ multiplier/ partial product/ key path delay/ chip area consumption分类
信息技术与安全科学引用本文复制引用
陈海民,李峥,谢铁顿..基于Radix-4Booth编码的乘法器优化设计[J].计算机工程,2012,38(1):233-235,3.基金项目
国家自然科学基金资助项目(61072047) （61072047）
郑州市创新型科技人才队伍建设工程基金资助项目(096SYJH21099) （096SYJH21099）
现代通信国家重点实验室基金资助项目(9140C1106021006) （9140C1106021006）
