计算机工程2012，Vol.38Issue(1)：268-269,272,3.DOI:10.3969/j.issn.1000-3428.2012.01.088
基于预缓冲机制的低功耗指令Cache
Low-power Instruction Cache Based on Predict Buffer Mechanism
摘要
Abstract
This paper designs an instruction Cache based on Predict Buffer(PB) mechanism to reduce the energy consumption of on-chip Cache of the processor. It can make instruction needed by processor hit in buffer mostly by PB control component predict, thus power dissipation of instruction Cache can be avoided. Simulation result of seven benchmarks shows that PB mechanism can save more than 23.23% power and improve performance by 7.53%.关键词
微处理器/低功耗/指令Cache/预缓冲/SimpleScalar仿真器Key words
microprocessor/ low-power/ instruction Cache/ Predict Buffer(PB)/ SimpleScalar simulator分类
信息技术与安全科学引用本文复制引用
王冶,张盛兵,王党辉..基于预缓冲机制的低功耗指令Cache[J].计算机工程,2012,38(1):268-269,272,3.基金项目
国家自然科学基金资助项目(60736012) （60736012）
