计算机工程与科学2012，Vol.34Issue(2)：62-66,5.DOI:10.3969/j.issn.1007-130X.2012.02.012
占空比优化的1.25GHz CMOS锁相环
1.25GHz CMOS PLL Withthe Duty Optimizing Technique
摘要
Abstract
In high-speed SerDes with the half rate structure, the duty of the clock is seriously impor tant, which is the decisive factor for unit intervals. In this article, a 1. 25GHz ring oscillator PLL is es tablished on the 0. 13 μm CMOS process, in which a duty balance circuit is integrated. The result of tes ting shows the stable output clock is 1. 25GHz, and the duty is within the range of 49. 86~51. 21% , and the mean duty is 51. 21%.关键词
半速率/高速串行接口/锁相环/占空比平衡/互补相位调节Key words
half-rate/SerDes/PLL/duty balance/coupling phase adjustment分类
信息技术与安全科学引用本文复制引用
马卓,郭阳,谢伦国..占空比优化的1.25GHz CMOS锁相环[J].计算机工程与科学,2012,34(2):62-66,5.基金项目
新世纪优秀人才支持计划资助项目 （）
